Research from the Nanoscale Imaging and Transport Lab led by Prof. Georges Pavlidis points to a lower-cost way to keep next-generation power electronics cool.
Francis Vasquez received the Best On-Site Poster Award in the component-level thermal management track at IEEE ITherm 2026, held May 26–29 in Orlando, Florida. He competed against 60 other students in the poster competition. His poster, “Impact of Die Substrate Properties on Peak Temperature of AlGaN HEMTs via Packaged-Level Simulation,” describes how to manage heat in a new class of high-power transistors.
Vasquez and fellow lab member Dominic Myren traveled to Orlando with the Nanoscale Imaging and Transport Lab, led by Dr. Georges Pavlidis, to present the group’s latest results on thermal management of microelectronics.
Why heat is the problem
Electric vehicles need faster charging, and AI data centers consume enormous amounts of power. Traditional silicon microchips are reaching their physical limits under those demands. The industry is turning to ultra-wide bandgap semiconductors such as aluminum gallium nitride, which allow smaller, faster, and more efficient devices that can operate at higher voltages.
The trade-off is heat. These high-power transistors generate so much of it that, without good cooling, they can fail early and become unreliable.
A cheaper path, and a thermal bottleneck
To make these devices affordable, the team is building them on sapphire, which costs about one-fifth as much as silicon carbide, the material commonly used today (based on 8-inch commercial wafers). Sapphire has a drawback, though: it conducts heat poorly, so it tends to trap it.
The work is part of the project “Advancing DoD High Power Systems: Transition of High Al% AlGaN from Lab to Fab,” carried out in collaboration with Analog Devices Inc. The goal is a device that delivers 50 watts of power while staying below 175 °C.
What the team found
Vasquez’s simulations showed that fine-tuning the microscopic layers inside the transistor does little to lower peak temperature in large commercial devices. The biggest gains come from the sapphire and the packaging around the chip:
- Thinner sapphire: Reducing the substrate to 300 micrometers (about 0.3 millimeters) raised the device’s power output by 37%, from 43 to 59 watts, in the baseline model.
- Better thermal interface materials: The material that bonds the chip package to the heat sink is the next critical choice. Metal-filled greases and graphene pads are promising options for limiting temperature rise.
What’s next
With the core thermal strategy validated at ITherm, the team will focus on miniaturization. They want to find out how small the device’s active area can get while the low-cost sapphire substrate stays thermally stable.
